1. Field of the Invention
The present invention generally relates to a semiconductor device and a method of processing the semiconductor device. More particularly, this invention relates to a semiconductor device including an alignment pattern and a method of processing the semiconductor device.
2. Description of the Related Art
Normally, multiple alignment patterns are provided on a wafer that is to be diced into chips (hereafter, a wafer where multiple semiconductor integrated circuits are formed is called a semiconductor device). Such alignment patterns are used by a semiconductor manufacturing apparatus, such as an exposure apparatus or a laser trimming apparatus, to align a semiconductor device. A semiconductor manufacturing apparatus detects an alignment pattern on a semiconductor device using an image recognition device and a camera and aligns the semiconductor device based on the detected alignment pattern. In this process, if the contrast of the alignment pattern is low, it is difficult to accurately align the semiconductor device.
FIG. 11 is a plan view of a portion of a conventional semiconductor device 100. The portion corresponds to the imaging area of an image recognition camera of a laser trimming apparatus (not shown).
As shown in FIG. 11, the semiconductor device 100 includes a semiconductor substrate 101, semiconductor integrated circuits 102, and an alignment pattern 103. The semiconductor substrate 101 includes semiconductor integrated circuit forming areas E and a scribe area F that separates the semiconductor integrated circuit forming areas E from each other. The semiconductor integrated circuits 102 are formed on the semiconductor integrated circuit forming areas E of the semiconductor substrate 101.
The alignment pattern 103 is provided for each portion of the semiconductor device 100 which portion corresponds to the imaging area of the image recognition camera of the laser trimming apparatus and is formed to cover almost the entire area of one of the semiconductor integrated circuit forming areas E in the portion. In other words, multiple alignment patterns 103 are provided on the semiconductor substrate 101. As the alignment pattern 103, for example, a test element group (TEG) pattern, which has high contrast, may be used.
One disadvantage of the semiconductor device 100 is that since each alignment pattern 103 occupies one semiconductor integrated circuit forming area E, the number of semiconductor integrated circuits 102 that can be formed on one semiconductor substrate 101 is reduced.
FIG. 12 is a plan view of a portion of another conventional semiconductor device 110 that has been proposed to solve the above problem. The portion corresponds to the imaging area of an image recognition camera of a laser trimming apparatus (not shown).
In FIG. 12, the same reference numbers are used for the components corresponding to those of the semiconductor device 100 shown in FIG. 11.
As shown in FIG. 12, the semiconductor device 110 includes a semiconductor substrate 101, semiconductor integrated circuits 102, and an alignment pattern 111. The alignment pattern 111 is provided for each portion of the semiconductor device 110 which portion corresponds to the imaging area of the image recognition camera of the laser trimming apparatus and is formed on a part of a scribe area F. As the material of the alignment pattern 111, for example, aluminum (Al) may be used (see, for example, patent document 1). As is clear from FIG. 12, this configuration improves the efficiency of use of space.
[Patent Document 1] Japanese Patent Application Publication No. 2000-323576
However, when the size of the semiconductor integrated circuits 102 of the semiconductor device 110 becomes small, the width W5 of the scribe area F becomes small and, accordingly, the width W6 of the alignment pattern 111 becomes small. If the alignment pattern 111 becomes very thin, the intensity of light reflected from the alignment pattern 111 becomes low and, as a result, it becomes difficult to detect the position of the alignment pattern 111.